SH7604 Datasheet, PDF (195/633 Pages) Hitachi Semiconductor – Hardware Manual

7.5.9 Phase Shift by PLL
The signals for synchronous DRAM interfaces change in the SH7604 at the rising edge of the
internal clock. Read data is fetched on the falling edge of an internal clock. Sampling of the
signals input by the synchronous DRAM and output of the read data, however, starts at the rising
edge of the external clock (figure 7.28).
When the internal clock of the SH7604 and external clock are synchronized, signal transmission
from the SH7604 to the synchronous DRAM has a 1 cycle margin. The transmission of read data
from the synchronous DRAM to the SH7604, however, is much tighter: only 1/2 cycle, including
the synchronous DRAM access time. When a clock system is connected without a means of
synchronization such as an on-chip PLL, transmission from the SH7604 to the synchronous
DRAM takes 1 cycle less the delay time of the clock system and transmission from the
synchronous DRAM to the SH7604 takes 1/2 cycle plus the clock system delay time. The clock
system delay time depends on the power supply voltage, temperature, and manufacturing variance,
so it has a fairly wide range. When the phase of the internal clock of the SH7604 is delayed using
a PLL that delays the phase 90 degrees relative to external clocks, transmission from the SH7604
to the synchronous DRAM and transmission from the SH7604 to the synchronous DRAM each
take 3/4 cycle.
Given this, using a clock whose phase is shifted 90 degrees from the external clock using a PLL as
the internal clock can ensure a margin of safety.
When using a PLL, it is important to note that synchronous DRAM does not contain an on-chip
PLL. When using the external clock input clock mode, instability in the clock supplied from
outside can cause shifts in phase, so a synchronization settling time in the SH7604’s on-chip PLL
is needed to equalize the SH7604’s internal clock and the external clock. During this
synchronization settling time, the internal clock of the synchronous DRAM and the internal clock
of the SH7604 will not always operate in perfect synchronization. To ensure the synchronous
DRAM and SH7604 operate properly, be sure that the external clock supplied is not unstable.
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