SH7604 Datasheet, PDF (175/633 Pages) Hitachi Semiconductor – Hardware Manual

SH7604
A10
A1
CKIO
CKE
CSn
RAS/CE
CAS/OE
RD/WR
D15
D0
CASLH/DQMLU/WE1
CASLL/DQMLL/WE0
256 k × 16-bit
synchronous
DRAM
A9
A0
CLK
CKE
CS
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 7.14 Synchronous DRAM 16-bit Device Connection
7.5.2 Address Multiplexing
Addresses are multiplexed according to the MCR’s address multiplex specification bits AMX2–
AMX0 and size specification bit SZ so that synchronous DRAMs can be connected directly
without an external multiplex circuit. Table 7.4 shows the relationship between the multiplex
specification bits and bit output to the address pins.
A26–A14 and A0 always output the original value regardless of multiplexing.
When SZ = 0, the data width on the synchronous DRAM side is 16 bits and the LSB of the
device’s address pins (A0) specifies word address. The A0 pin of the synchronous DRAM is thus
connected to the A1 pin of the SH7604, the rest of the connection proceeding in the same order,
beginning with the A1 pin to the A2 pin.
When SZ = 1, the data width on the synchronous DRAM side is 32 bits and the LSB of the
device’s address pins (A0) specifies longword address. The A0 pin of the synchronous DRAM is
thus connected to the A2 pin of the SH7604, the rest of the connection proceeding in the same
order, beginning with the A1 pin to the A3 pin.
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