SH7604 Datasheet, PDF (257/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 1: TE
0
1
Description
DMA has not ended or was aborted
Cleared by reading 1 from the TE bit and then writing 0
DMA has ended normally (by TCR = 0)
(Initial value)
• Bit 0—DMA Enable Bit (DE): Enables or disables DMA transfers. In auto-request mode, the
transfer starts when this bit or the DME bit in DMAOR is set to 1. The NMIF and AE bits in
DMAOR and the TE bit must be all set to 0. In external request mode or on-chip peripheral
module request mode, the transfer begins when the DMA transfer request is received from the
relevant device or on-chip peripheral module, provided this bit and the DME bit are set to 1.
As with the auto-request mode, the TE bit and the NMIF and AE bits in DMAOR must be all
set to 0. The transfer can be stopped by clearing this bit to 0. The DE bit is initialized to 0 by a
reset and in standby mode. Its value is retained during a module standby.
Bit 0: DE
0
1
Description
DMA transfer disabled
DMA transfer enabled
(Initial value)
9.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1)
Bit: 31
30
29
…
11
10
9
8
Bit name: —
—
—
…
—
—
—
—
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
DMA vector number registers 0 and 1 (VCRDMA0, VCRDMA1) are 32-bit read/write registers
that set the DMAC transfer-end interrupt vector number. Only the lower eight bits of the 32 are
effective. They are written as 32-bit values, including the upper 24 bits. Write the initial values to
the upper 24 bits. These bits are initialized to H'000000XX (last eight bits are undefined) by a
reset and in standby mode. Values are retained during a module standby.
• Bits 31 to 8—Reserved: These bits always read 0. The write value should always be 0.
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