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| SH7604 Datasheet, PDF (556/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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Tp
Tpw
Tr
Trw
Tc1
Tw
Tc2
CKIO
Address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
WAIT
tWTS tWTH
RAS,
CE
CAS,
OE
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.54 Pseudo-SRAM Bus Cycle (TRP = 2 Cycles, RCD = 2 Cycles, 1 Wait)
540
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