SH7604 Datasheet, PDF (158/633 Pages) Hitachi Semiconductor – Hardware Manual

7.2.4 Individual Memory Control Register (MCR)
Bit: 15
14
13
12
11
10
9
8
Bit name: TRP RCD TRWL TRAS1 TRAS0 BE RASD —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 7
6
5
4
3
2
1
0
Bit name: AMX2 SZ AMX1 AMX0 RFSH RMD
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
R
R
The TRP, RCD, TRWL, TRAS1–TRAS0, BE, RASD, AMX2–AMX0 and SZ bits are initialized
after a power-on reset. Do not write to them thereafter. When writing to them, write the same
values as they are initialized to. Do not access any space other than CS2 and CS3 until the register
initialization ends.
• Bit 15—RAS Precharge Time (TRP): When DRAM is connected, specifies the minimum
number of cycles after RAS is negated before the next assert. When pseudo-SRAM is
connected, specifies the minimum number of cycles after CE is negated before the next assert.
When synchronous DRAM is connected, specifies the minimum number of cycles after
precharge until a bank active command is output. See section 7.5, Synchronous DRAM
Interface, for details.
Bit 15: TRP
0
1
Description
1 cycle
2 cycles
(Initial value)
• Bit 14—RAS-CAS Delay (RCD): When DRAM is connected, specifies the number of cycles
after RAS is asserted before CAS is asserted. When pseudo-SRAM is connected, specifies the
number of cycles after CE is asserted before BS is asserted. When synchronous DRAM is
connected, specifies the number of cycles after a bank active (ACTV) command is issued until
a read or write command (READ, READA, WRIT, WRITA) is issued.
Bit 14: RCD
0
1
Description
1 cycle
2 cycles
(Initial value)
142