 English |
|
|
|
|
|
|
|
| SH7604 Datasheet, PDF (438/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
| |||
| ◁ |
CKIO
Upper
address
Lower
address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
Tr
tAD
Tc
Td1
Td2
Td3
Td4
tAD
tAD
tAD
tAD
tAD
tBSD
tCSD1
tRWD
tBSD
tBSD
tCSD1
tRWD
tRSD1
tDQMD
tDQMD
tDACD1
tRDS3 tRDH4
tRDS3 tRDH4
tRDS3 tRDH4
tRDS3 tRDH4
tDACD2 tDACD2 tDACD2 tDACD2
tDACD1 tDACD1 tDACD1
WAIT
RAS,
CE
CAS,
OE
tRASD1 tRASD1
tCASD1 tCASD1
tRASD1
tCASD1 tCASD1
CKE
Notes: 1. The dotted line shows the waveform when synchronous DRAM in another CS space
is accessed.
2. The DACKn waveform shown is for the case where active-high has been specified.
Figure 15.20 Synchronous DRAM Read Bus Cycle
(RCD = 1 Cycle, CAS Latency = 1 Cycle, Bursts = 4, PLL On)
422
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese