SH7604 Datasheet, PDF (426/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 15.7 Bus Timing With PLL On and 1/4 Cycle Delay [Mode 1, 5]
(Conditions: V_CC = 5.0 V ±10%, Ta = –20 to +75°C)
Item
Address delay time
BS delay time
CS delay time 1
CS delay time 2
Read/write delay time
Read strobe delay time 1
Read data setup time 1
Read data setup time 3
(SDRAM)
Read data hold time 2
Read data hold time 4
(SDRAM)
Read data hold time 5
(DRAM)
Read data hold time 6
(PSRAM)
Read data hold time 7
(interrupt vector)
Write enable delay time
Write data delay time 1
Write data hold time 1
Data buffer on time
Data buffer off time
Symbol
t_AD
t_BSD
t_CSD1
t_CSD2
t_RWD
t_RSD1
t_RDS1
t_RDS3
t_RDH2
t_RDH4
t_RDH5
t_RDH6
t_RDH7
t_WED1
t_WDD
t_WDH1
t_DON
t_DOF
Min
Max
Unit Figures
1/4 tcyc + 3 1/4 tcyc + 18 ns 15.14, 15.20, 15.40,
15.52, 15.66, 15.68
—
1/4 tcyc + 21 ns 15.14, 15.20, 15.40,
15.52, 15.66
—
1/4 tcyc + 21 ns 15.14, 15.20, 15.40,
15.52, 15.66
—
3/4 tcyc + 21 ns 15.14, 15.66
1/4 tcyc + 3 1/4 tcyc + 18 ns 15.14, 15.20, 15.40,
15.52, 15.66
—
3/4 tcyc + 16 ns 15.14, 15.40, 15.52,
15.66, 15.68
1/4 tcyc + 10 —
ns 15.14, 15.40, 15.52,
15.66, 15.68
1/4 tcyc + 8 —
ns 15.20
0
—
ns 15.14, 15.66
0
—
ns 15.20
0
—
ns 15.40
0
—
ns 15.52
0
—
ns 15.68
3/4 tcyc + 3 3/4 tcyc + 18 ns
1/4 tcyc + 3 1/4 tcyc + 18 ns
1/4 tcyc + 3 —
ns
—
1/4 tcyc + 18 ns
—
1/4 tcyc + 18 ns
15.14, 15.15, 15.52,
15.53
15.15, 15.27, 15.41,
15.53
15.15, 15.27, 15.41,
15.53
15.15, 15.27, 15.41,
15.53
15.15, 15.27, 15.41,
15.53
410