SH7604 Datasheet, PDF (224/633 Pages) Hitachi Semiconductor – Hardware Manual

Master
mode
CKIO
BRLS
BGR
BS
RD
IVECF
CSn
RAS
CAS
RD/WR
WEn
A26–A0
CKE
WAIT
D31–D0
Buffer
control
CK EN
CK EN
DIR
Partial-share
master mode
CKIO
BREQ
BACK
BS
RD
IVECF
CSn
RAS
CAS
RD/WR
WEn
A26–A0
CKE
WAIT
D31–D0
Synchronous
DRAM
CK
CKE
CS
RAS
CAS
WE
DQMxx
An
Dn
ROM
CS
OE
An
Dn
Interfaces with
other devices
BS
RD
IVECF
CS
RD/WEn
WEn
An
WAIT
Dn
Synchronous
DRAM
CK
CKE
CS
RAS
CAS
WE
DQMxx
An
Dn
ROM
CS
OE
An
Dn
Figure 7.52 Connection between Master and Partial-Share Master Devices
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