SH7604 Datasheet, PDF (625/633 Pages) Hitachi Semiconductor – Hardware Manual

BSC
Bit
7 to 0
Bit Name
Wait control of areas 3
to 0 (W31–W00)
Value
Description
During basic cycle
W31 W30
W21 W20
W11 W10
W01 W00
0 0 External wait input disabled without waits
0 1 External wait input enabled with one wait
1 0 External wait input enabled with two waits
1 1 Complies with the long wait specification of bus control
register 1 (BCR1)
External wait input is enabled (Initial value)
When area 3 is DRAM
W31 W30
0 0 1 CAS assert cycle
0 1 2 CAS assert cycles
1 0 3 CAS assert cycles
1 1 Reserved (setting prohibited)
When area 2 or 3 is synchronous DRAM
W31 W30
W21 W20
0 0 1 CAS latency cycle
0 1 2 CAS latency cycles
1 0 3 CAS latency cycles
1 1 4 CAS latency cycles (Initial value)
When area 3 is pseudo-SRAM
W31 W30
0 0 2 cycles from BS signal assertion to end of cycle
0 1 3 cycles from BS signal assertion to end of cycle
1 0 4 cycles from BS signal assertion to end of cycle
1 1 Reserved (setting prohibited)
Individual memory control register
(MCR)
H'FFFFFFEC
16/32
Bit
Item
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name
TRAS TRAS
TRP RCD TRWL 1
0 BE RASD — AMX2 SZ AMX1 AMX0 RFSH RMD — —
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R
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