 English |
|
|
|
|
|
|
|
| SH7604 Datasheet, PDF (517/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
| |||
| ◁ |
CKIO
A26âA0
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
WAIT
RAS,
CE
CAS,
OE
T1
tAD
T2
tAD
tBSD
tCSD1
tRWD
tBSD
tCSD2
tRWD
tRSD1
tWED1
tRSD1
tWED1 tAH1
tDON
tWDD
tDACD1
tWDH1
tDOF
tDACD2
Notes: 1.
2.
CKE
The dotted line shows the waveform when synchronous DRAM is connected.
The DACKn waveform shown is for the case where active-high has been
specified.
Figure 16.15 Basic Write Cycle (No Waits, PLL On)
501
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese