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| SH7604 Datasheet, PDF (520/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
A26âA0
T1
Tw
T2
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
WAIT
tWTS tWTH
RAS,
CE
CAS,
OE
CKE
Notes: 1. The dotted line shows the waveform when synchronous DRAM is connected.
2. The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.18 Basic Bus Cycle (1 Wait Cycle)
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