SH7604 Datasheet, PDF (213/633 Pages) Hitachi Semiconductor – Hardware Manual

Tp
CKIO
CS3
BS
CE
OE/RFSH
RD
WEn
Trr
Trc
Trc
Tre
Figure 7.43 Self-Refresh
7.7.6 Power-On Sequence
When pseudo-SRAM is used after the power is turned on, there is a requirement for a waiting
period during which accesses cannot be performed (100 µs minimum) followed by the prescribed
number of dummy auto-refresh cycles (usually 8). The bus state controller does not perform any
special operations for the power-on reset, so the required power-on sequence must be implemented
by the initialization program executed after a power-on reset.
7.8 Burst ROM Interface
Set the BSTROM bit in BCR1 to set the CS0 space for connection to burst ROM. The burst ROM
interface is used to permit fast access to ROMs that have the nibble access function. Figure 7.44
shows the timing of nibble accesses to burst ROM. Set for two wait cycles. The access is basically
the same as an ordinary access, but when the first cycle ends, only the address is changed. The
CS0 signal is not negated, enabling the next access to be conducted without the T1 cycle required
for ordinary space access. From the second time on, the T1 cycle is omitted, so access is 1 cycle
faster than ordinary accesses. Currently, the nibble access can only be used on 4-address ROM.
This function can only be utilized for word or longword reads to 8-bit ROM and longword reads to
16-bit ROM. Mask ROMs have slow access speeds and require 4 instruction fetches for 8-bit
widths and 16 accesses for cache fills. Limited support of nibble access was thus added to alleviate
this problem. When connecting to an 8-bit width ROM, a maximum of 4 consecutive accesses are
performed; when connecting to a 16-bit width ROM, a maximum of 2 consecutive accesses are
performed. Figure 7.45 shows the relationship between data width and access size. For cache fills
and DMAC 16-byte transfers, longword accesses are repeated 4 times.
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