SH7604 Datasheet, PDF (283/633 Pages) Hitachi Semiconductor – Hardware Manual

Clock
DACK
Address
bus
Pre-
charge
DMAC address
DMAC read or write
(basic timing)
Figure 9.31 DACK Output in Normal Pseudo-SRAM Accesses (AM = 1 or 0)
Clock
DACK
Address
bus
DMAC address
DMAC read or write
(basic timing)
Figure 9.32 DACK Output in Pseudo-SRAM Burst Accesses
(Same Row Address, AM = 1 or 0)
Clock
DACK
Address
bus
Pre-
charge
DMAC address
DMAC read or write
(basic timing)
Figure 9.33 DACK Output in Pseudo-SRAM Burst Accesses
(Different Row Address, AM = 1 or 0)
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