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| SH7604 Datasheet, PDF (536/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Upper
address
Lower
address
BS
Tp
Tpw
Tmw
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
tRWD
tRWD
DACKn
WAIT
RAS,
CE
CAS,
OE
tRASD1
tRASD1
CKE
Figure 16.34 Synchronous DRAM Mode Register Write Cycle (TRP = 2 Cycles)
520
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