SH7604 Datasheet, PDF (101/633 Pages) Hitachi Semiconductor – Hardware Manual

CKIO
CS0–CS3
BS
A3–A0
IVECF
RD/WR
RD
D7–D0
WAIT
Interrupt priority level
Vector number input
Figure 5.4 External Vector Mode Interrupt Vector Fetch Cycle
5.2.4 On-chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following 6 on-chip
peripheral modules:
• Division unit (DIVU)
• Direct memory access controller (DMAC)
• Serial communication interface (SCI)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Free-running timer (FRT)
A different interrupt vector is assigned to each interrupt source, so the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers A and B (IPRA
and IPRB). On-chip peripheral module interrupt exception handling sets the interrupt mask level
bits (I3–I0) in the status register (SR) to the priority level value of the on-chip peripheral module
interrupt that was accepted.
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