SH7604 Datasheet, PDF (133/633 Pages) Hitachi Semiconductor – Hardware Manual

The BRCR register:
1. Determines whether to use channels A and B as two independent channels or as sequential
conditions.
2. Selects SH7000 series compatible mode or SH7604 mode.
3. Selects whether to break before or after instruction execution during the instruction fetch cycle.
4. Enables or disables the external bus.
5. Selects whether to include the data bus in channel B comparison conditions.
It also has a condition-match flag that is set when conditions match. A power-on reset initializes
BRCR to H'0000. Its value is undefined after a manual reset.
• Bit 15—CPU Condition-Match Flag A (CMFCA): Set to 1 when CPU bus cycle conditions
included in the break conditions set for channel A are met. Not cleared to 0.
Bit 15: CMFCA
0
1
Description
Channel A CPU cycle conditions do not match, no user break interrupt
generated
(Initial value)
Channel A CPU cycle conditions have matched, user break interrupt
generated
• Bit 14—Peripheral Condition-Match Flag A (CMFPA): Set to 1 when peripheral bus cycle
conditions (on-chip DMAC, or external bus cycle when external bus breaks are enabled)
included in the break conditions set for channel A are met. Not cleared to 0.
Bit 14: CMFPA
0
1
Description
Channel A peripheral cycle conditions do not match, no user break
interrupt generated
(Initial value)
Channel A peripheral cycle conditions have matched, user break
interrupt generated
• Bit 13—External Bus Break Enable (EBBE): Monitors the external bus master's address bus
when the bus is released, and includes the external bus master's bus cycle in the bus cycle
select conditions (CPA1, CPB1). External bus breaks are possible in the total master mode and
total slave mode. When the external bus break is enabled, set CPA1 in BBRA or CPB1 in
BBRB.
Bit 13: EBBE
0
1
Description
Chip-external bus cycle not included in break conditions
Chip-external bus cycle included in break conditions
(Initial value)
117