SH7604 Datasheet, PDF (619/633 Pages) Hitachi Semiconductor – Hardware Manual

DMAC
DMA transfer count registers 0 and H'FFFFFF88 (channel 0)
1 (TCR0 and TCR1)
H'FFFFFF98 (channel 1)
32
Item
Bit Name
Initial Value
R/W
Item
Bit Name
Initial Value
R/W
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———— ————
0 0 0 0 0 0 0 0 ———— ————
R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
23 to 0 (Transfer count
specification)
Description
Specifies the DMA transfer count (during a DMA transfer,
these bits indicate the remaining transfer count)
DMA channel control registers 0, 1 H'FFFFFF8C (channel 0)
(CHCR0, CHCR1)
H'FFFFFF9C (channel 1)
32
Bit
Item
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit Name — — — — — — — — — — — — — — — —
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
RRRR RRRR RRRR RRRR
Item
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name DM1 DM0 SM1 SM0 TS1 TS0 AR AM AL DS DL TB TA IE TE DE
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/ R/W
(W)*
Note: Only 0 can be written, after reading 1, to clear the flag.
Bit
14, 15
Bit Name
Destination address
mode bits 1, 0
(DM1, DM0)
Value
Description
0 0 Fixed destination address (Initial value)
0 1 Destination address is incremented (+1 for byte transfer
size, +2 for word transfer size, +4 for longword transfer
size, and +16 for 16-byte transfer size)
1 0 Destination address is decremented (–1 for byte transfer
size, –2 for word transfer size, –4 for longword transfer
size, and –16 for 16-byte transfer size)
1 1 Reserved (setting prohibited)
603