SH7604 Datasheet, PDF (177/633 Pages) Hitachi Semiconductor – Hardware Manual

Figure 7.15 shows an example of the basic cycle. Because a slower synchronous DRAM is
connected, setting WCR and MCR bits can extend the cycle. The number of cycles from the
ACTV command output cycle Tr to the READA command output cycle Tc can be specified by the
RCD bit in MCR. 0 specifies 1 cycle; 1 specifies 2 cycles. For 2 cycles, a NOP command issue
cycle Trw for the synchronous DRAM is inserted between the Tr cycle and the Tc cycle. The
number of cycles between the READA command output cycle Tc and the initial read data fetch
cycle Td1 can be specified independently for areas CS2 and CS3 between 1 cycle and 4 cycles
using the W21/W20 and W31/W30 bits in WCR. The CAS latency when using bus arbitration in
the partial-share master mode can be set differently for CS2 and CS3 spaces. The number of
cycles at this time corresponds to the number of CAS latency cycles of the synchronous DRAM.
When 2 cycles or more, a NOP command issue cycle Tw is inserted between the Tc cycle and the
Td1 cycle. The number of cycles in the precharge completion waiting cycle Tap is specified by the
TRP bit in MCR. When the CAS latency is 1, a Tap cycle of 1 or 2 cycles is generated. When the
CAS latency is 2 or more, a Tap cycle equal to the TRP specification – 1 is generated. During the
Tap cycle, no commands other than NOP are issued to the same bank. Figure 7.16 shows an
example of burst read timing when RCD is 1, W31/W30 is 01, and TRP is 1.
With the synchronous DRAM cycle, when the bus cycle starts in ordinary space access, the BS
signal asserted for 1 cycle is asserted in each of cycles Td1–Td4 for the purpose of the external
address monitoring described in the section on bus arbitration. When another CS space is accessed
after an synchronous DRAM read with a wait-between-buses specification of 0, the BS signal may
be continuously asserted. The address is updated every time data is fetched while burst reads are
being performed. The burst transfer unit is 16 bytes, so address updating affects A3–A1. The
access order follows the address order in 16-byte data transfers by the DMAC, but reading starts
from the address + 4 so that the last missed data in the fill operation after a cache miss can be read.
When the data width is 16 bits, 8 burst cycles are required for a 16-byte data transfer. The data
fetch cycle goes from Td1 to Td8. From Td1 to Td8, the BS signal is asserted in every cycle.
Synchronous DRAM CAS latency is up to 3 cycles, but the CAS latency of the bus state controller
can be specified up to 4. This is so that circuits containing latches can be installed between
synchronous DRAMs and the SH7604.
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