SH7604 Datasheet, PDF (297/633 Pages) Hitachi Semiconductor – Hardware Manual

• Burst Mode, Dual Mode, Level Detection
Transfer width: Byte, word, longword
Transfer bus mode: Burst mode
Transfer address mode: Single mode
DREQ detection method: Level detection
DACK output timing: DMAC read
Bus cycle: Basic bus cycle
Clock
DREQ
DACK
*
1st
acceptance
*
2nd
acceptance
*
3rd
acceptance
Bus
cycle
CPU
DMAC read
DMAC
invalid write
DMAC read
Note: Request detection (The points when the 1st and 2nd acceptances occur vary with the
type of wait.)
Figure 9.50 Timing of DREQ Pin Input Detection in Burst Mode with Level Detection (5)
Acknowledge signals for request signals are output 4 cycles later, at the soonest. Even when
the request signal is dropped within 0.5 cycle of the output of the acknowledge signal, the 2nd
request in figure 9.50 is accepted. This means that two DMA transfers are executed even when
the request for the 1st acknowledge signal drops out.
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