SH7604 Datasheet, PDF (118/633 Pages) Hitachi Semiconductor – Hardware Manual

IRL0
IRL1
IRL2
IRL3
Noise
canceler
Interrupt
controller
Interrupt
request
CPU
Pin level cleared
when interrupt is accepted
Interrupt
accepted
Figure 5.8 Interrupt Response Block Diagram
IRL3–IRL0
pin level
1111
1011 for
1 clock
due to
noise
1111
Noise canceler
output
1111
Level 2 interrupt
1101
Level 6 interrupt
1001
Cleared when interrupt is accepted
1101
1001
Interrupt request
to CPU
Interrupt acceptance
signal to CPU
Figure 5.9 Interrupt Response Timing Chart
102