SH7604 Datasheet, PDF (172/633 Pages) Hitachi Semiconductor – Hardware Manual

When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 7.12 shows WAIT signal sampling. A 2-cycle wait is specified as a software wait.
The sampling is performed when the Tw state shifts to the T2 state, so there is no effect even when
the WAIT signal is asserted in the T1 cycle or the first Tw cycle. The WAIT signal is sampled at
the clock rise. External waits should not be inserted, however, into word accesses of devices (such
as ordinary space and burst ROM) that have an 8-bit bus width (byte-size devices). Control waits
in such cases with software only.
T1
Tw
Wait states
from WAIT
signal input
Tw
Twx
T2
Clock
A26–A0
CSn
RD/WR
Read
RD
D31–D0
Write
WEn
D31–D0
WAIT
BS
Figure 7.12 Wait State Timing of Ordinary Space Access
(Wait States from WAIT Signal)
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