SH7604 Datasheet, PDF (604/633 Pages) Hitachi Semiconductor – Hardware Manual

WDT
Watchdog timer control/status
register (WTCSR)
H'FFFFFE80
8 (read)
16 (write)
Bit
Item
7
6
5
4
Bit Name OVF WT/IT TME
—
3
2
1
0
—
CKS2 CKS1 CKS0
Initial Value
0
0
0
1
1
0
0
0
R/W
R/(W)* R/W
R/W
—
—
R/W
R/W
R/W
Note: WTCSR differs from other registers in being more difficult to write. See section 12.2.4,
Register Access, for details.
Bit
Bit Name
7 Overflow flag (OVF)
6 Timer mode select
(WT/IT)
5 Timer enable (TME)
2 to 0 Clock select 2 to 0
(CKS2 to CKS0)
Value
Description
0 No overflow of WTCNT in interval timer mode (Initial
value)
Cleared by reading OVF, then writing 0 in OVF
1 WTCNT overflow in interval timer mode
0 Interval timer mode: Interval timer interrupt (ITI) request
to the CPU when WTCNT overflows (Initial value)
1 Watchdog timer mode: WDTOVF signal is output
externally when WTCNT overflows
0 Timer disabled: WTCNT is initialized to H'00 and count-
up stops (Initial value)
1 Timer enabled: WTCNT starts counting
A WDTOVF signal or interrupt is generated when
WTCNT overflows
CKS2 CKS1 CKS0 Clock Source
Overflow Interval
(φ = 28.7 MHz)
0
0
0 φ/2 (Initial value) 17.8µs
0
0
1 φ/64
570.8µs
0
1
0 φ/128
1.1ms
0
1
1 φ/256
2.2ms
1
0
0 φ/512
4.5ms
1
0
1 φ/1024
9.1ms
1
1
0 φ/4096
35.5ms
1
1
1 φ/8192
73.0ms
588