SH7604 Datasheet, PDF (607/633 Pages) Hitachi Semiconductor – Hardware Manual

DIVU
Division control register (DVCR) H'FFFFFF08
16/32
Item
Bit Name
Initial Value
R/W
Item
Bit Name
Initial Value
R/W
31 30 29 28
————
0000
RRRR
15 14 13 12
————
0000
RRRR
Bit
27 26 25 24 23 22 21 20
———— ————
0000 0000
RRRR RRRR
11 10 9 8 7 6 5 4
———— ————
0000 0000
RRRR RRRR
19 18 17 16
————
0000
RRRR
3210
OVF
— — IE OVF
0000
R R R/W R/W
Bit
Bit Name
1 OVF interrupt enable
(OVFIE)
0 Overflow flag (OVF)
Value
Description
0 Disables interrupt request (OVFI) caused by OVF
(Initial value)
1 Enables interrupt request (OVFI) caused by OVF
0 No overflow has occurred (Initial value)
1 Overflow has occurred
Dividend register H (DVDNTH) H'FFFFFF10
32
Item
Bit Name
Initial Value
R/W
Item
Bit Name
Initial Value
R/W
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 1 (Dividend setting)
Description
Set with the upper 32 bits of the dividend used for 64-bit/32-
bit division operations
591