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| SH7604 Datasheet, PDF (473/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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Tp
CKIO
Address
Tr
Tc1
Tw
Twx
Tc2
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
WAIT
tWTS tWTH tWTS tWTH
RAS,
CE
CAS,
OE
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 15.55 Pseudo-SRAM Bus Cycle
(TRP = 1 Cycle, RCD = 1 Cycle, External Wait Input)
457
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