SH7604 Datasheet, PDF (307/633 Pages) Hitachi Semiconductor – Hardware Manual

10.2.4 Vector Number Setting Register DIV (VCRDIV)
Bit: 31
30
29
…
19
18
17
16
Bit name: —
—
—
…
—
—
—
—
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
Bit: 15
14
13
…
3
2
1
0
Bit name:
…
Initial value: —
—
—
…
—
—
—
—
R/W: R/W R/W R/W
…
R/W R/W R/W R/W
Vector number setting register DIV (VCRDIV) is a 32-bit read/write register, but is also 16-bit
accessible. The destination vector number is set in VCRDIV when an interrupt occurs in the
division unit due to an overflow or underflow. Values can be set in the 16 bits from bit 15 to bit 0,
but only the last 7 bits (bits 6–0) are valid. Always set 0 for the 9 bits from bit 15 to bit 7.
VCRDIV is not initialized by a power-on reset or manual reset, in standby mode, or during
module standbys.
• Bits 31 to 7: Reserved. These bits always read 0. The write value should always be 0.
• Bits 6 to 0: Interrupt Vector Number. Sets the interrupt destination vector number. Only the 7
bits 6–0 are valid (as the vector number).
10.2.5 Dividend Register H (DVDNTH)
Bit: 31
30
39
…
3
2
1
0
Bit name:
…
Initial value: —
—
—
…
—
—
—
—
R/W: R/W R/W R/W
…
R/W R/W R/W R/W
Dividend register H (DVDNTH) is a 32-bit read/write register in which the upper 32 bits of the
dividend used for 64 bit ÷ 32 bit division operations are written. When a division operation is
executed, the value set as the dividend is lost and the remainder written here at the end of the
operation. The initial value of DVDNTH is undefined, and its value is also undefined after a
power-on reset or manual reset, in standby mode, and during in module standbys. When the
DVDNT register is set with a dividend value, the previous DVDNTH value is lost and the MSB of
the DVDNT register is extended to all bits in the DVDNTH register.
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