SH7604 Datasheet, PDF (346/633 Pages) Hitachi Semiconductor – Hardware Manual

12.4 Usage Notes
12.4.1 Contention between WTCNT Write and Increment
If a timer counter clock pulse is generated during the T3 state of a write cycle to WTCNT, the
write takes priority and the timer counter is not incremented (figure 12.8).
φ
Address
WTCNT address
Internal write
signal
WTCNT input
clock
WTCNT
N
M
Counter write data
Figure 12.8 Contention between WTCNT Write and Increment
12.4.2 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may
increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
12.4.3 Switching between Watchdog Timer and Interval Timer Mode
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
330