SH7604 Datasheet, PDF (541/633 Pages) Hitachi Semiconductor – Hardware Manual

CKIO
Upper
address
Lower
address
BS
T_r
T_c
T_ap
CSn
RD/WR
WE
RD
WEn
CASxx
DQMxx
D31–D0
DACKn
WAIT
t_WDD
t_DON
t_DOF
t_WDH1
t_DACD3
RAS
CE
CAS
OE
Notes: 1.
2.
CKE
Dotted lines show the waveforms when synchronous DRAM in another CS space
is accessed.
The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.39 Synchronous DRAM Write Bus Cycle
(RCD = 1 Cycle, TRWL = 1 Cycle, PLL Off)
525