SH7604 Datasheet, PDF (233/633 Pages) Hitachi Semiconductor – Hardware Manual

CPU pipeline stage
EX
MA
WB
EX
MA
EX
Cache address bus
Address A Address B
Cache tag comparison
Cache data bus
Address A Address B
Data array read
EX: Instruction execution
MA: Memory access
WB: Write-back
Figure 8.3 Read Access in Case of a Cache Hit
When a cache miss occurs, the way for replacement is determined using the LRU information, and
the read address from the CPU is written in the address array for that way. Simultaneously, the
valid bit is set to 1. Since the 16 bytes of data for replacing the data array are simultaneously read,
the address on the cache address bus is output to the internal address bus and 4 longwords are read
consecutively. Access starts with whatever address output to the internal address bus will make the
longword that contains the address to be read from the cache come last as the byte address within
the line as the order + 4. The data read on the internal data bus is written sequentially to the cache
data array. When the last data is written to the cache data array, it is simultaneously written to the
cache data bus and the read data is sent to the CPU.
The internal address bus and internal data bus also function as pipelines, just like the cache bus.
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