SH7604 Datasheet, PDF (618/633 Pages) Hitachi Semiconductor – Hardware Manual

DMAC
DMA source address registers 0 H'FFFFFF80 (channel 0)
and 1 (SAR0 and SAR1)
H'FFFFFF90 (channel 1)
32
Item
Bit Name
Initial Value
R/W
Item
Bit Name
Initial Value
R/W
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Description
31 to 0 (Transfer source address These bits specify the DMA transfer source address
specification)
DMA destination address registers H'FFFFFF84 (channel 0)
0 and 1 (DAR0 and DAR1)
H'FFFFFF94 (channel 1)
32
Item
Bit Name
Initial Value
R/W
Item
Bit Name
Initial Value
R/W
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 0 (Transfer destination
address specification)
Description
These bits specify the DMA transfer destination address
602