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| SH7604 Datasheet, PDF (537/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Trr
Trc1
Trc2
Tre
Tnop
Upper
address
Lower
address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
tAD
tRWD
tAD
tCSD1
tBSD
tRWD
tCSD1
DACKn
WAIT
RAS,
CE
CAS,
OE
tRASD1
tRASD1
tCASD1
tCASD1
tRASD1
Note:
CKE
A precharge cycle always precedes the auto-refresh cycle by the number of cycles
specified by TRP.
Figure 16.35 Synchronous DRAM Auto-Refresh Cycle (TRAS = 2 Cycles)
521
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