SH7604 Datasheet, PDF (399/633 Pages) Hitachi Semiconductor – Hardware Manual

Constraints on DMAC Use:
• When using an external clock source for the serial clock, update TDR with the DMAC, and
then after twenty system clock cycles or more elapse, input a transmit clock. If a transmit clock
is input in the first four states after TDR is written, an error may occur (figure 13.22).
• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as an activation source using the resource select bit (RS) in the channel
control register (CHCR).
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: During external clock operation, an error may occur if t is 4 states or less.
Figure 13.22 Example of Clocked Synchronous Transmission with DMAC
Cautions for Clocked Synchronous External Clock Mode:
• Set TE = RE = 1 only when external clock SCK is 1.
• Do not set TE = RE = 1 until at least four clock cycles after external clock SCK has changed
from 0 to 1.
• When receiving, RDRF is set to 1 when RE is cleared to 0 2.5–3.5 clocks after the rising edge
of the RxD D7 bit SCK input, but it cannot be copied to RDR.
Caution for Clocked Synchronous Internal Clock Mode: When receiving, RDRF is set to 1
when RE is cleared to 0 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but it
cannot be copied to RDR.
383