SH7604 Datasheet, PDF (28/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 1.1 Pin Functions (cont)
Pin No.
FP-144 TBP-176 Pin Name
I/O
—
P15 NC
—
—
N14 NC
—
73
M13 CS1
O
74
N15 CS2
O
75
M14 CS3
O
76
L12
BS
I/O
77
M15 RD/WR
I/O
78
L13
V_SS
I
79
L14
RAS/CE
O
80
L15
CAS/OE
O
81
K12
CASHH/DQMUU/WE3 O
82
K13
CASHL/DQMUL/WE2 O
83
K15
CASLH/DQMLU/WE1 O
84
K14
V_CC
I
85
J12
CASLL/DQMLL/WE0 O
86
J13
V_SS
I
87
J15
RD
O
88
J14
CKE
O
89
H12 WAIT
I
90
H13 NC
—
91
H15
V_SS
I
92
H14 BACK/BRLS
I
93
G12 BREQ/BGR
O
94
G13 WDTOVF
O
95
G15 FTOB
O
96
G14
V_CC
I
Pin Description
Reserved pin (leave unconnected)
Reserved pin (leave unconnected)
Chip select 1
Chip select 2
Chip select 3
Bus cycle start
Read/write
Ground
RAS for DRAM and synchronous DRAM, CE
for pseudo-SRAM
CAS for synchronous DRAM, OE for
pseudo-SRAM
Most significant byte selection signal for
memory
Second byte selection signal for memory
Third byte selection signal for memory
Power
Least significant byte selection signal for
memory
Ground
Read pulse
Synchronous DRAM clock enable control
Hardware wait request
Reserved pin (leave unconnected)
Ground
Bus acknowledge in slave mode, bus
request in master mode
Bus request in slave mode, bus grant in
master mode
Watchdog timer output
Free-running timer output B
Power
12