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| SH7604 Datasheet, PDF (456/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Upper
address
Lower
address
BS
CSn
RD/WR
WE
RD
WEn
CASxx
DQMxx
D31âD0
DACKn
Tr
tAD
Tc
Td1
Td2
Td3
Td4
tAD
tAD
tAD
tAD
tAD
tBSD
tBSD
tBSD
tCSD1
tRWD
tCSD1
tRWD
tRSD2
tDQMD
tDACD1
tRDS2
tDQMD
tRDH3
tRDH3
tRDH3 tRDH3
tRDS2
tRDS2
tRDS2
tDACD3 tDACD3 tDACD3 tDACD3
tDACD1 tDACD1 tDACD1
WAIT
RAS
CE
CAS
OE
tRASD1 tRASD1
tCASD1 tCASD1
tRASD1
tCASD1 tCASD1
CKE
Notes: 1. The dotted line shows the waveform when synchronous DRAM in another CS space
is accessed.
2. The DACKn waveform shown is for the case where active-high has been specified.
Figure 15.38 Synchronous DRAM Read Bus Cycle
(RCD = 1 Cycle, CAS Latency = 1 Cycle, TRP = 1 Cycle, Bursts = 4, PLL Off)
440
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