 English |
|
|
|
|
|
|
|
| SH7604 Datasheet, PDF (446/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
| |||
| ◁ |
CKIO
Upper
address
Lower
address
BS
CSn
RD/WR
WE
RD
WEn
CASxx
DQMxx
D31âD0
DACKn
Tr
Trw
Tc
Trwl
Tap
tCSD1
tDACD1
WAIT
RAS
CE
CAS
OE
tRASD1
tCASD1
tRASD1
CKE
Notes: 1. Dotted lines show the waveforms when synchronous DRAM in another CS space
is accessed.
2. The DACKn waveform shown is for the case where active-high has been specified.
Figure 15.28 Synchronous DRAM Write Bus Cycle
(RCD = 2 Cycles, TRWL = 2 Cycles)
430
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese