SH7604 Datasheet, PDF (606/633 Pages) Hitachi Semiconductor – Hardware Manual

DIVU
Divisor register (DVSR)
H'FFFFFE00
32
Item
Bit Name
Initial Value
R/W
Item
Bit Name
Initial Value
R/W
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 0 (Written with divisor)
Description
Used to write the divisor for the operation
Dividend register L for 32-bit
division (DVDNT)
H'FFFFFE04
32
Item
Bit Name
Initial Value
R/W
Item
Bit Name
Initial Value
R/W
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
———— ———— ———— ————
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 0 (Dividend setting)
Description
Set with the 32-bit dividend used for 32-bit/32-bit division
operations
590