SH7604 Datasheet, PDF (219/633 Pages) Hitachi Semiconductor – Hardware Manual

externally. Writing from the CPU always produces a write cycle externally since the write-through
system is used by the SH7604 for the cache. When an external bus address monitor is not specified
by the user break controller, the internal bus that connects the CPU, DMAC and on-chip
peripheral modules can operate in parallel to the external bus. This means that both read and write
accesses from CPU to on-chip peripheral modules and from DMAC to on-chip peripheral module
are possible. If an external bus address monitor is specified, the internal bus will be used for
address monitoring when the bus is passed to the external bus master, so accesses to on-chip
peripheral modules by the CPU and DMAC must wait for the bus to be returned.
7.10.1 Master Mode
Master mode processors keep the bus unless they receive a bus request. When a bus release
request (BRLS) assertion (low level) is received from an external device, buses are released and a
bus grant (BGR) is asserted (low level) as soon as the bus cycle being executed is completed.
When it receives a negated (high level) BRLS signal, indicating that the slave has released the bus,
it negates the BGR (to high level) and begins using the bus. When the bus is released, all output
and I/O signals related to the bus interface are changed to high impedance, except for the CKE
signal for the synchronous DRAM interface, the BGR signal for bus arbitration, and DMA transfer
control signals DACK0 and DACK1.
When the DRAM or pseudo-SRAM has finished precharging, the bus is released. The
synchronous DRAM also issues a precharge command to the active bank or banks. After this is
completed, the bus is released.
The specific bus release sequence is as follows. First, the bus use enable signal is asserted
synchronously with the fall of the clock. Half a cycle later, the address bus and data bus become
high impedance synchronous with the rise of the clock. Thereafter the bus control signals (BS,
CSn, RAS, CAS, WEn, RD, RD/WR, IVECF) become high impedance with the fall of the clock.
All of these signals are negated at least 1.5 cycles before they become high impedance. Sampling
for bus request signals occurs at the clock fall.
The sequence when the bus is taken back from the slave is as follows. When the negation of BRLS
is detected at a clock fall, BGR is immediately negated and the master simultaneously starts to
drive the bus control signals. The address bus and data bus are driven starting at the next clock
rise. The bus control signals are asserted and the bus cycle actually starts from the same clock rise
at which the address and data signals are driven, at the earliest. Figure 7.48 shows the timing of
bus arbitration in master mode.
203