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| SH7604 Datasheet, PDF (555/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
Tp
Tr
tAD
Tc1
Tc2
tAD
tBSD
tBSD
tCSD1
tCSD1
tRWD
tRWD
tRSD1
tRSD1
tWED1
tWED1
tWDD
tDON
tWED1
tWED1
tDOF
tWDH1
tDACD1
tDACD2
WAIT
RAS,
CE
CAS,
OE
tCED1
tOED1
tCED1
tCED1
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.53 Pseudo-SRAM Write Cycle
(PLL On, TRP = 1 Cycle, RCD = 1 Cycle, No Waits)
539
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