SH7604 Datasheet, PDF (105/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit:
Bit name:
Initial value:
R/W:
15
DIVU
IP3
0
R/W
14
DIVU
IP2
0
R/W
13
DIVU
IP1
0
R/W
12
DIVU
IP0
0
R/W
11
DMAC
IP3
0
R/W
10
DMAC
IP2
0
R/W
9
DMAC
IP1
0
R/W
8
DMAC
IP0
0
R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: WDT WDT WDT WDT
—
—
—
—
IP3
IP2
IP1
IP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W
R
R
R
R
• Bits 15 to 12—Division Unit (DIVU) Interrupt Priority Level (DIVUIP3–DIVUIP0): These
bits set the division unit (DIVU) interrupt priority level. There are four bits, so levels 0–15 can
be set.
• Bits 11 to 8—DMA Controller Interrupt Priority Level (DMACIP3–DMACIP0): These bits set
the DMA controller (DMAC) interrupt priority level. There are four bits, so levels 0–15 can be
set. The same level is set for both DMAC channels. When interrupts occur simultaneously,
channel 0 has priority.
• Bits 7 to 4—Watchdog Timer (WDT) Interrupt Priority Level (WDTIP3–WDTIP0): These bits
set the watchdog timer (WDT) interrupt priority level and bus state controller (BSC) interrupt
priority level. There are four bits, so levels 0–15 can be set. When WDT and BSC interrupts
occur simultaneously, the WDT interrupt has priority.
• Bits 3 to 0—Reserved: These bits always read 0. The write value should always be 0.
5.3.2 Interrupt Priority Level Setting Register B (IPRB)
Interrupt priority level setting register B (IPRB) is a 16-bit read/write register that assigns priority
levels from 0 to 15 to on-chip peripheral module interrupts. IPRB is initialized to H'0000 by a
reset. It is not initialized in standby mode.
89