SH7604 Datasheet, PDF (57/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 2.17 System Control Instructions (cont)
Instruction
Instruction Code
Operation
Execu-
tion
T
States Bit
STS MACH,Rn 0000nnnn00001010 MACH → Rn
1
—
STS MACL,Rn 0000nnnn00011010 MACL → Rn
1
—
STS PR,Rn
0000nnnn00101010 PR → Rn
1
—
STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn)
1
—
STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn)
1
—
STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn)
1
—
TRAPA #imm
11000011iiiiiiii PC/SR → stack area, (imm) → 8
—
PC
Note:
The number of execution states before the chip enters the sleep mode.
Instruction states: The values shown for the execution states are minimums. The actual
number of states may be increased when:
• Contention occurs between instruction fetch and data access
• The destination register of the load instruction (memory → register) and the register used
by the next instruction are the same.
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