SH7604 Datasheet, PDF (114/633 Pages) Hitachi Semiconductor – Hardware Manual

Program execution
state
Interrupt
No
generated?
Yes
NMI?
No
Yes
User break?
No
Save SR to stack
Save PC to stack
Copy accepted
interrupt level to I3–I0
Read vector number*
Yes
Level 15
No
interrupt?
Yes
Yes
I3 to I0 ≤
level 14?
Level 14
interrupt?
Yes
No Yes
I3 to I0 ≤
level 13?
No
Level 1 ^No
interrupt?
Yes
No Yes
I3 to I0 =
level 0?
No
Read exception
vector table
Branch to exception
service routine
I3-I0: Status register interrupt mask bits.
Note: The vector number is only read from an external source when an external
vector number is specified for the IRL interrupt vector number.
Figure 5.5 Interrupt Sequence Flowchart
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