SH7604 Datasheet, PDF (41/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 2.8 Addressing Modes and Effective Addresses (cont)
Addressing
Mode
PC relative
(cont)
Instruction
Format
Effective Addresses Calculation
Rn
The effective address is the register PC value
plus Rn.
PC
+
PC + Rn
Equation
PC + Rn
Immediate
#imm:8
#imm:8
#imm:8
Rn
The 8-bit immediate data (imm) for the TST,
—
AND, OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV,
—
ADD, and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
—
instruction is zero-extended and quadrupled.
2.3.3 Instruction Formats
Table 2.9 shows instruction formats and source and destination operands. The meaning of the
operands depends on the instruction code. The following symbols are used in the table:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
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