SH7604 Datasheet, PDF (159/633 Pages) Hitachi Semiconductor – Hardware Manual

• Bit 13—Write-Precharge Delay (TRWL): When the synchronous DRAM is not in the bank
active mode, this bit specifies the number of cycles between the write cycle and the start-up of
the auto-precharge. The timing from this point to the point at which the next command can be
issued is calculated within the bus state controller. In bank active mode, this bit specifies the
period for which the precharge command is disabled after the write command (WRIT) is
issued. This bit is ignored when memory other than synchronous DRAM is connected.
Bit 13: TRWL
0
1
Description
1 cycle
2 cycles
(Initial value)
• Bits 12 and 11—CAS-Before-RAS Refresh RAS Assert Time (TRAS1–TRAS0): The RAS
assertion width for DRAM is TRAS; the OE width for pseudo-SRAM is TRAS + 1 cycle.
After an auto-refresh command is issued, the synchronous DRAM does not issue a bank active
command for TRAS + 2 cycles, regardless of the TRP bit setting. For synchronous DRAMs,
there is no RAS assertion period, but there is a limit for the time from the issue of a refresh
command until the next access. This value is set to observe this limit. Commands are not
issued for TRAS + 1 cycle when self-refresh is cleared.
Bit 12: TRAS1
0
1
Bit 11: TRAS0
0
1
0
1
Description
2 cycles
3 cycles
4 cycles
Reserved (do not set)
(Initial value)
• Bit 10—Burst Enable (BE)
Bit 10: BE
0
1
Description
Burst disabled
(Initial value)
High-speed page mode during DRAM interfacing is enabled. Data is
continuously transferred in static column mode during pseudo-SRAM
interfacing. During synchronous DRAM access, burst operation is
always enabled regardless of this bit.
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