SH7604 Datasheet, PDF (292/633 Pages) Hitachi Semiconductor – Hardware Manual

Transfer width: 16-byte
Transfer bus mode: Cycle-steal mode
Transfer address mode: Dual mode
DREQ detection method: Level detection
DACK output timing: DMAC write cycle
Bus cycle: Basic bus cycle
Clock
*
DREQ
1st acceptance
DACK
*
*
2nd acceptance 3rd acceptance
2 cycles 2 cycles
A1 A2 A3 A4
1st 16-byte transfer
*
4th acceptance
2 cycles
B1 B2 B3 B4
2nd 16-byte transfer
Bus
cycle
CPU
DMAC
read 1
Invalid
write
DMAC
write 2
DMAC
write 4
CPU
DMAC
read 4
DMAC
write 1
DMAC
write 3
CPU
CPU
DMAC
read 4
DMAC
write 1
DMAC
write 3
CPU
DMAC
read 1
Invalid
write
DMAC
write 2
DMAC
write 4
Note: Request detection
Figure 9.44 Timing of DREQ Pin Input Detection in Cycle Steal Mode
with Level Detection (4)
For 16-byte transfers, DACK signals are output at all consecutive writes (figure 9.44). The
acknowledge signals are A1, A2, A3, A4, B1, B2, B3, B4, ….
The second transfer request can be detected 2 cycles after output of acknowledge signal A1. The
third transfer request is detected at A3, that is, 2 cycles after output of the third acknowledge
signal of the first transfer. The fourth transfer request is detected 2 cycles after output of B3.
Requests thereafter are detected 2 cycles after the third acknowledge signal of each transfer, as
with the fourth transfer.
Note: When transferring alternately on channels 0 and 1 by round robin or the like, the next
request signal is detected only 2 cycles after the first acknowledge signal of each transfer
(figure 9.45).
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