SH7604 Datasheet, PDF (274/633 Pages) Hitachi Semiconductor – Hardware Manual

Bus
state
CPU ^{DMAC DMAC DMAC DMAC DMAC DMAC DMAC} CPU
ch1
ch1
ch0
ch1
ch0
ch1
ch1
ch0
ch1
ch0
CPU
DMAC ch1
Burst mode
DMAC ch1 and ch0
Cycle-steal
DMAC ch1
Burst mode
CPU
Note: Priority is ch0 > ch1, ch1 is in burst mode, ch0 is in cycle-steal mode
Figure 9.12 Bus Status when Multiple Channels are Operating
9.3.5 Number of Bus Cycles
The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus
control register (BCR1) and wait state control register (WCR) of the bus state controller just as it
is when the CPU is the bus master.
9.3.6 DMA Transfer Request Acknowledge Signal Output Timing
DMA transfer request acknowledge signal DACKn is output synchronous to the DMAC address
output specified by the channel control register AM bit of the address bus. The timing is normally
to have the acknowledge signal become valid when the DMA address output begins and become
invalid 0.5 cycles before the address output ends. (See figure 9.11.) The output timing of the
acknowledge signal varies with the settings of the connected memory space. The output timing of
acknowledge signals in the memory spaces is shown in figure 9.13.
Clock
DACK
Address bus
CPU
0.5 cycles
DMAC
Figure 9.13 Example of DACK Output Timing
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