SH7604 Datasheet, PDF (212/633 Pages) Hitachi Semiconductor – Hardware Manual

The number of OE assert cycles for auto-refresh is specified by the TRAS bit in MCR. As with
ordinary accesses, the specification of the precharge time from OE negation to the next CE assert
follows the setting of the TRP bit in MCR.
Tp
Trr
Trc
Trc
Tre
CKIO
CS3
BS
CE
OE/RFSH
RD
WEn
Figure 7.42 Auto-Refresh
The self-refresh mode is initiated in the pseudo-SRAM when the RFSH signal stays low for a
prescribed period of time. A self-refresh is started by setting the RMODE and RFSH bits to 1.
During the self-refresh, the pseudo-SRAM cannot be accessed. To clear self-refreshing, set either
the RMODE or RFSH bit to 0. After self-refresh mode is cleared, issuing of commands is
inhibited for 1 auto-refresh cycle. If more time than this is required to return from self-refresh,
write the program so that there are no accesses to the pseudo-SRAM, including auto-refreshes,
during this period. Figure 7.43 shows the self-refresh timing. After self-refreshing is cleared,
immediately set the pseudo-SRAM so that auto-refresh is performed in the correct interval. This
ensures correct self-refresh clearing and data retention. When time is required between clearing
the self-refreshing and initiating the auto-refresh mode, this time must be reflected in the initial
RTCNT setting.
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