SH7604 Datasheet, PDF (515/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 16.9 Bus Timing With PLL Off (CKIO Output) [Mode 2] (cont)
(Conditions: V_CC = 3.0 to 5.5 V, Ta = –20 to +75°C)
Item
Symbol Min
Max
Unit Figures
WAIT setup time
t_WTS
20
—
ns 16.19, 16.43, 16.55,
16.67, 16.70
WAIT hold time
t_WTH
10
—
ns 16.19, 16.43, 16.55,
16.67, 16.70
RAS delay time 1 (SDRAM) t_RASD1 —
25
ns 16.38
RAS delay time 3 (DRAM) t_RASD3 3
25
ns 16.47
CAS delay time 1 (SDRAM) t_CASD1 —
25
ns 16.38
CAS delay time 3 (DRAM) t_CASD3 3
25
ns 16.47
DQM delay time
t_DQMD
—
25
ns 16.38
CKE delay time
t_CKED
—
33
ns 16.37
CE delay time 2
t_CED2
3
25
ns 16.60
OE delay time 2
t_OED2
—
25
ns 16.60
IVECF delay time
t_IVD
—
25
ns 16.69
Address input setup time^* t_ASIN
25
—
ns 16.71
Address input hold time^*
t_AHIN
10
—
ns 16.71
BS input setup time^*
t_BSS
25
—
ns 16.71
BS input hold time^*
t_BSH
10
—
ns 16.71
Read/write input setup time^* t_RWS
25
—
ns 16.71
Read/write input hold time^* t_RWH
10
—
ns 16.71
Data buffer on time
t_DON
—
25
ns 16.17, 16.39, 16.48,
16.61
Data buffer off time
t_DOF
—
25
ns 16.17, 16.39, 16.48,
16.61
Note: When the external addresses monitor function is used, the PLL must be on.
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