SH7604 Datasheet, PDF (336/633 Pages) Hitachi Semiconductor – Hardware Manual

12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the WDT.
ITI
(interrupt
request signal)
WDTOVF
Internal
reset signal*
Interrupt
control
Overflow
Clock
Clock
select
Reset
control
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal
clock
RSTCSR
TCNT
TCSR
Module bus
Bus
interface
WDT
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
RSTCSR: Reset control/status register
Note: The internal reset signal can be generated by a register setting. The type of reset can be
selected (power-on or manual reset).
Figure 12.1 WDT Block Diagram
12.1.3 Pin Configuration
Table 12.1 shows the pin configuration.
Table 12.1 Pin Configuration
Pin
Abbreviation I/O
Watchdog timer overflow WDTOVF
O
Function
Outputs the counter overflow signal in
watchdog mode
320