SH7604 Datasheet, PDF (81/633 Pages) Hitachi Semiconductor – Hardware Manual

Section 4 Exception Handling
4.1 Overview
4.1.1 Types of Exception Handling and Priority Order
Exception handling is initiated by four sources: resets, address errors, interrupts, and instructions
(table 4.1). When several exception handling sources occur at once, they are processed according
to priority.
Table 4.1 Types of Exception Handling and Priority Order
Exception Source
Priority
Reset
Power-on reset
High
Manual reset
Address
error
CPU address error
DMA address error
Interrupt NMI
User break
IRL (IRL1–IRL15 (set with IRL3, IRL2, IRL1, IRL0 pins))
On-chip peripheral modules Division unit (DIVU)
Direct memory access controller (DMAC)
Watchdog timer (WDT)
Compare match interrupt (part of the bus
state controller)
Serial communication interface (SCI)
16-bit free-running timer (FRT)
Instructions Trap instruction (TRAPA)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly following a delayed Low
branch instruction^*1 or instructions that rewrite the PC^*2)
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
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