SH7604 Datasheet, PDF (135/633 Pages) Hitachi Semiconductor – Hardware Manual

• Bit 5—Reserved: This bit always reads 0. The write value should always be 0.
• Bit 4—Sequence Condition Select (SEQ): Selects whether to handle the channel A and B
conditions independently or sequentially.
Bit 4: SEQ
0
1
Description
Channel A and B conditions compared independently (Initial value)
Channel A and B conditions compared sequentially (channel A, then
channel B)
• Bit 3—Data Break Enable B (DBEB): Selects whether to include data bus conditions in the
channel B break conditions.
Bit 3: DBEB
0
1
Description
Data bus conditions not included in the channel B conditions
(Initial value)
Data bus conditions included in the channel B conditions
• Bit 2—Instruction Break Select (PCBB): Selects whether to place the channel B instruction
fetch cycle break before or after instruction execution.
Bit 2: PCBB
0
1
Description
Places the channel B instruction fetch cycle break before instruction
execution
(Initial value)
Places the channel B instruction fetch cycle break after instruction
execution
• Bits 1 and 0—Reserved: These bits always read 0. The write value should always be 0.
119