SH7604 Datasheet, PDF (355/633 Pages) Hitachi Semiconductor – Hardware Manual

• Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the built-in baud rate generator. Four clock sources are available. φ/4, φ/16, φ/64 and
φ/256. For further information on the clock source, bit rate register settings, and baud rate, see
section 13.2.8, Bit Rate Register.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
φ/4
φ/16
φ/64
φ/256
(Initial value)
13.2.6 Serial Control Register (SCR)
The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock
output in asynchronous mode, enables/disables interrupts, and selects the transmit/receive clock
source. The CPU can always read and write to SCR. SCR is initialized to H'00 by a reset and in
standby and module standby modes.
Bit: 7
6
5
4
3
2
1
0
Bit name: TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1 due to transfer of serial transmit data from TDR to TSR.
Bit 7: TIE
0
1
Description
Transmit-data-empty interrupt request (TXI) is disabled (Initial value)
The TXI interrupt request can be cleared by reading TDRE after it has
been set to 1, then clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TXI) is enabled
• Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt
(RXI) requested when the receive data register full bit (RDRF) in the serial status register
(SSR) is set to 1 due to transfer of serial receive data from RSR to RDR. It also enables or
disables receive-error interrupt (ERI) requests.
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